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1 ltc1418 low power, 14-bit, 200ksps adc with serial and parallel i/o output code 4096 0 1.0 inl (lsbs) 0.5 0 0.5 1.0 8192 1418 ta02 12288 16384 typical inl curve the ltc ? 1418 is a low power, 200ksps, 14-bit a/d converter. data output is selectable for 14-bit parallel or serial format. this versatile device can operate from a single 5v or 5v supply. an onboard high performance sample-and-hold, a precision reference and internal tim- ing minimize external circuitry requirements. the low 15mw power dissipation is made even more attractive with two user selectable power shutdown modes. the ltc1418 converts 0v to 4.096v unipolar inputs from a single 5v supply and 2.048v bipolar inputs from 5v supplies. dc specs include 1.25lsb inl, 1lsb dnl and no missing codes over temperature. outstanding ac performance includes 82db s/(n + d) and 94db thd at the nyquist input frequency of 100khz. the flexible output format allows either parallel or serial i/o. the spi/microwire tm compatible serial i/o port can oper- ate as either master or slave and can support clock frequen- cies from dc to 10mhz. a separate convert start input and a data ready signal (busy) allow easy control of conversion start and data transfer. descriptio n u features n single supply 5v or 5v operation n sample rate: 200ksps n 1.25lsb inl and 1lsb dnl max n power dissipation: 15mw (typ) n parallel or serial data output n no missing codes over temperature n power shutdown: nap and sleep n external or internal reference n differential high impedance analog input n input range: 0v to 4.096v or 2.048v n 81.5db s/(n + d) and C 94db thd at nyquist n 28-pin narrow pdip and ssop packages typical applicatio n u , ltc and lt are registered trademarks of linear technology corporation. microwire is a trademark of national semiconductor corporation. n remote data acquisition n battery operated systems n digital signal processing n isolated data acquisition systems n audio and telecom processing n medical instrumentation applicatio n s u s/h 14 buffer 8k 10 f 10 f refcomp a in a in + v ref 4.096v 5v ltc1418 14-bit adc selectable serial/ parallel port d13 dgnd 1418 ta01 v ss (0v or 5v) agnd ser/par d5 d4 (extclkin) d3 (sclk) d2 (clkout) d1 (d out ) d0 (ext/int) v dd timing and logic 2.5v reference busy cs rd convst shdn 1 f low power, 200khz, 14-bit sampling a/d converter
2 ltc1418 absolute m axi m u m ratings w ww u (notes 1, 2) supply voltage (v dd ) ................................................. 6v negative supply voltage (v ss ) bipolar operation only ........................... C 6v to gnd total supply voltage (v dd to v ss ) bipolar operation only ....................................... 12v analog input voltage (note 3) unipolar operation .................. C 0.3v to (v dd + 0.3v) bipolar operation........... (v ss C 0.3v) to (v dd + 0.3v) digital input voltage (note 4) unipolar operation ................................ C 0.3v to 10v bipolar operation.........................(v ss C 0.3v) to 10v digital output voltage unipolar operation .................. C 0.3v to (v dd + 0.3v) bipolar operation........... (v ss C 0.3v) to (v dd + 0.3v) power dissipation .............................................. 500mw operation temperature range ltc1418c................................................ 0 c to 70 c ltc1418i ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c package/order i n for m atio n w u u order part number consult factory for military grade parts. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view g package 28-lead plastic ssop n package 28-lead narrow pdip 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a in + a in v ref refcomp agnd d13 (msb) d12 d11 d10 d9 d8 d7 d6 dgnd v dd v ss busy cs convst rd shdn ser/par d0 (ext/int) d1 (d out ) d2 (clkout) d3 (sclk) d4 (extclkin) d5 ltc1418acg LTC1418ACN ltc1418aig ltc1418ain ltc1418cg ltc1418cn ltc1418ig ltc1418in cc hara terist ics co u verter ltc1418 ltc1418a parameter conditions min typ max min typ max units resolution (no missing codes) l 13 14 bits integral linearity error (note 7) l 0.8 2 0.5 1.25 lsb differential linearity error l 0.7 1.5 0.35 1 lsb offset error (note 8) l 5 20 2 10 lsb full-scale error internal reference 10 60 20 60 lsb external reference = 2.5v 5 30 5 15 lsb full-scale tempco i out(ref) = 0, internal reference, commercial l 15 10 45 ppm/ c i out(ref) = 0, internal reference, industrial 20 ppm/ c i out(ref) = 0, external reference 5 1 ppm/ c with internal reference (notes 5, 6) unless otherwise noted. put u i a a u log symbol parameter conditions min typ max units v in analog input range (note 9) 4.75v v dd 5.25v (unipolar) l 0 to 4.096 v 4.75v v dd 5.25v, C 5.25v v ss C 4.75v (bipolar) l 2.048 v i in analog input leakage current cs = high l 1 m a c in analog input capacitance between conversions (sample mode) 25 pf during conversions (hold mode) 5 pf t acq sample-and-hold acquisition time commercial l 300 1000 ns industrial l 300 1000 ns (note 5) t jmax = 110 c, q ja = 95 c/ w (g) t jmax = 110 c, q ja = 100 c/ w (n)
3 ltc1418 (note 5) symbol parameter conditions min typ max units s/(n + d) signal-to-noise plus distortion ratio 97.5khz input signal l 79 81.5 db thd total harmonic distortion 100khz input signal, first 5 harmonics l C 94 C 86 db sfdr spurious free dynamic range 100khz input signal l 86 95 db imd intermodulation distortion f in1 = 97.7khz, f in2 = 104.2khz C 90 db full power bandwidth 5 mhz full linear bandwidth s/(n + d) 3 77db 0.5 mhz accuracy ic dy u w a (note 5) i ter al refere ce characteristics u uu parameter conditions min typ max units v ref output voltage i out = 0 2.480 2.500 2.520 v v ref output tempco i out = 0, commercial l 10 45 ppm/ c i out = 0, industrial 20 ppm/ c v ref line regulation 4.75v v dd 5.25v 0.05 lsb/ v C 5.25v v ss C 4.75v 0.05 lsb/ v v ref output resistance 0.1ma ? i out ? 0.1ma 8 k w (note 5) digital i puts a n d outputs u u symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd l 10 m a c in digital input capacitance 1.4 pf v oh high level output voltage v dd = 4.75v, i o = C 10 m a 4.74 v v dd = 4.75v, i o = C 200 m a l 4.0 v v ol low level output voltage v dd = 4.75v, i o = 160 m a 0.05 v v dd = 4.75v, i o = 1.6ma l 0.10 0.4 v i oz hi-z output leakage d13 to d0 v out = 0v to v dd , cs high l 10 m a c oz hi-z output capacitance d13 to d0 cs high (note 9) l 15 pf i source output source current v out = 0v C 10 ma i sink output sink current v out = v dd 10 ma symbol parameter conditions min typ max units v dd positive supply voltage (notes 10, 11) 4.75 5.25 v v ss negative supply voltage (note 10) bipolar only (v ss = 0v for unipolar) C 4.75 C 5.25 v i dd positive supply current unipolar, rd high (note 5) l 3.0 4.3 ma bipolar, rd high (note 5) l 3.9 4.5 ma nap mode shdn = 0v, cs = 0v (note 12) 570 m a sleep mode shdn = 0v, cs = 5v (note 12) 2 m a i ss negative supply current bipolar, rd high (note 5) l 1.4 1.8 ma nap mode shdn = 0v, cs = 0v (note 12) 0.1 m a sleep mode shdn = 0v, cs = 5v (note 12) 0.1 m a p dis power dissipation unipolar l 15.0 21.5 mw bipolar l 26.5 31.5 mw (note 5) power require e ts w u
4 ltc1418 ti i g characteristics w u (note 5) symbol parameter conditions min typ max units f sample(max) maximum sampling frequency l 200 khz t conv conversion time l 3.4 4 m s t acq acquisition time l 0.3 1 m s t acq + t conv acquisition plus conversion time l 3.7 5 m s t 1 cs to rd setup time (notes 9, 10) l 0ns t 2 cs to convst setup time (notes 9, 10) l 40 ns t 3 cs to shdn setup time to ensure nap mode (notes 9, 10) l 40 ns t 4 shdn - to convst wake-up time from nap mode (note 10) 500 ns t 5 convst low time (notes 10, 11) l 40 ns t 6 convst to busy delay cl = 25pf l 35 70 ns t 7 data ready before busy - 20 35 ns l 15 ns t 8 delay between conversions (note 10) l 500 ns t 9 wait time rd after busy - l C5 ns t 10 data access time after rd c l = 25pf 15 30 ns l 40 ns c l = 100pf 20 40 ns l 55 ns t 11 bus relinquish time 820 ns commercial l 25 ns industrial l 30 ns t 12 rd low time l t 10 ns t 13 convst high time 40 ns t 14 delay time, sclk to d out valid c l = 25pf (note 9) l 35 70 ns t 15 time from previous data remain valid after sclk c l = 25pf (note 9) l 15 25 ns f sclk shift clock frequency (notes 9, 10) 0 12.5 mhz f extclkin external conversion clock frequency (notes 9, 10) 0.03 4.5 mhz t dextclkin delay time, convst to external conversion clock input (notes 9, 10) 533 m s t h sclk sclk high time (notes 9, 10) 10 ns t l sclk sclk low time (notes 9, 10) 20 ns t h extclkin extclkin high time (notes 9, 10) 250 ns t l extclkin extclkin low time (notes 9, 10) 250 ns the l denotes specifications which apply over the full operating temperature range; all other limits and typicals t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with dgnd and agnd wired together (unless otherwise noted). note 3: when these pin voltages are taken below v ss or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss or above v cc without latchup. note 4: when these pin voltages are taken below v ss they will be clamped by internal diodes. this product can handle input currents greater than 100ma below v ss without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, v ss = 0v or C 5v, f sample = 200khz, t r = t f = 5ns unless otherwise specified. note 6: linearity, offset and full-scale specifications apply for a single- ended input with a in C grounded. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 8: bipolar offset is the offset voltage measured from C 0.5lsb when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. note 9: guaranteed by design, not subject to test. note 10: recommended operating conditions. note 11: the falling edge of convst starts a conversion. if convst returns high at a critical point during the conversion, it can create small errors. for best performance ensure that convst returns high either within 2.1 m s after the conversion starts or after busy rises. note 12: pins 16 (d4/extclkin), 17 (d3/sclk) and 20 (do/ext/int) at 0v or 5v. see power shutdown.
5 ltc1418 typical perfor m a n ce characteristics uw frequency (khz) 0 120 amplitude (db) 100 ?0 ?0 ?0 20 50 70 100 1418 g05 ?0 0 10 30 40 60 80 90 f sample = 200khz f in1 = 97.65625khz f in2 = 104.248046khz intermodulation distortion plot frequency (khz) 01030507090 amplitude (db) 0 20 40 60 80 100 120 20 40 60 80 1418 f02a 100 f sample = 200khz f in = 9.9609375khz sfdr = 99.32 sinad = 82.4 nonaveraged, 4096 point fft, input frequency = 10khz input frequency (hz) 10k spurious-free dynamic range (db) 100k 1m 1418 g04 0 20 40 60 80 100 120 s/(n + d) vs input frequency and amplitude input frequency (hz) signal/(noise + distortion) (db) 90 80 70 60 50 40 30 20 10 0 1k 100k 1m 1418 g01 10k v in = 60db v in = 0db v in = 20db frequency (khz) 01030507090 amplitude (db) 0 20 40 60 80 100 120 20 40 60 80 1418 f02b 100 f sample = 200khz f in = 97.509765khz sfdr = 94.29 sinad = 81.4 nonaveraged, 4096 point fft, input frequency = 100khz typical inl curve output code 4096 0 1.0 inl (lsbs) 0.5 0 0.5 1.0 8192 1418 ta02 12288 16384 output code 0 1.0 dnl error (lsbs) 0.5 0 0.5 1.0 4096 8192 1418 g06 12288 16384 differential nonlinearity vs output code input frequency (hz) amplitude (db below the fundamental) 0 20 40 60 80 100 120 1418 g03 1k 100k 1m 10k thd 2nd 3rd distortion vs input frequency spurious-free dynamic range vs input frequency signal-to-noise ratio vs input frequency input frequency (hz) signal-to -noise ratio (db) 1k 0 90 80 70 60 50 40 30 20 10 1418 g02 100k 1m 10k
6 ltc1418 typical perfor m a n ce characteristics uw frequency (hz) 1k distortion (db) 10k 100k 1418 g08 1m 10m 0 20 40 60 80 100 120 v ss v dd dgnd power supply feedthrough vs ripple frequency v dd supply current vs temperature (unipolar mode) v dd supply current vs sampling frequency (bipolar mode) sampling frequency (khz) 0 v dd supply current (ma) 50 100 150 200 1418 g15 250 300 5 4 3 2 1 0 input frequency (hz) 110 common mode rejection (db) 10k 100k 90 80 70 60 50 40 30 20 10 0 1418 g09 100 1k 1m input common mode rejection vs input frequency input offset voltage shift vs source resistance input source resistance ( ) change in offset voltage (lsb) 10 9 8 7 6 5 4 3 2 1 0 10 1k 10k 1m 1418 g10 100 100k temperature ( c) ?5 v dd supply current (ma) 75 1418 g12 ?0 150 ?5 0 25 50 100 125 5 4 3 2 1 0 v dd supply current vs temperature (bipolar mode) v ss supply current vs temperature (bipolar mode) sampling frequency (khz) 0 v ss supply current (ma) 50 100 150 200 1418 g16 250 300 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 v ss supply current vs sampling frequency (bipolar mode) temperature ( c) ?5 v ss supply current (ma) 75 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1418 g13 ?0 150 ?5 0 25 50 100 125 v dd supply current vs sampling frequency (unipolar mode) sampling frequency (khz) 0 v dd supply current (ma) 50 100 150 200 1418 g14 250 300 5 4 3 2 1 0 temperature ( c) ?5 v dd supply current (ma) 75 5 4 3 2 1 0 1418 g11 ?0 150 ?5 0 25 50 100 125
7 ltc1418 pi n fu n ctio n s uuu a in + (pin 1): positive analog input. a in C (pin 2): negative analog input. v ref (pin 3): 2.50v reference output. bypass to agnd with 1 m f. refcomp (pin 4): 4.096v reference bypass pin. bypass to agnd with 10 m f tantalum in parallel with 0.1 m f ceramic. agnd (pin 5): analog ground. d13 to d6 (pins 6 to 13): three-state data outputs (parallel). d13 is the most significant bit. dgnd (pin 14): digital ground for internal logic. tie to agnd. d5 (pin 15): three-state data output (parallel). d4 (extclkin) (pin 16): three-state data output (parallel). conversion clock input (serial) when pin 20 (ext/int) is tied high. d3 (sclk) (pin 17): three-state data output (parallel). data clock input (serial). d2 (clkout) (pin 18): three-state data output (parallel). conversion clock output (serial). d1 (d out ) (pin 19): three-state data output (parallel). serial data output (serial). d0 (ext/int) (pin 20): three-state data output (parallel). conversion clock selector (serial). an input low enables the internal conversion clock. an input high indicates an external conversion clock will be assigned to pin 16 (extclkin). ser/par (pin 21): data output mode. shdn (pin 22): power shutdown input. low selects shutdown. shutdown mode selected by cs. cs = 0 for nap mode and cs = 1 for sleep mode. rd (pin 23): read input. this enables the output drivers when cs is low. convst (pin 24): conversion start signal. this active low signal starts a conversion on its falling edge. cs (pin 25): chip select. this input must be low for the adc to recognize the convst and rd inputs. cs also sets the shutdown mode when shdn goes low. cs and shdn low select the quick wake-up nap mode. cs high and shdn low select sleep mode. busy (pin 26): the busy output shows the converter status. it is low when a conversion is in progress. v ss (pin 27): negative supply, C 5v for bipolar operation. bypass to agnd with 10 m f tantalum in parallel with 0.1 m f ceramic. analog ground for unipolar operation. v dd (pin 28): 5v positive supply. bypass to agnd with 10 m f tantalum in parallel with 0.1 m f ceramic. test circuits 1k c l dbn dgnd a) hi-z to v oh and v ol to v oh c l dbn 1k 5v b) hi-z to v ol and v oh to v ol dgnd 1418 tc01 load circuits for access timing load circuits for output float delay 1k 30pf dbn a) v oh to hi-z 30pf dbn 1k 5v b) v ol to hi-z 1418 tc02
8 ltc1418 fu n ctio n al block diagra uu w 14-bit capacitive dac comp ref amp 2.5v ref 8k refcomp 4.096v 2.5v c sample c sample ? ? d13 d0 busy control logic d2/(clkout) internal clock shdn d0 (ext/int) d4 (extclkin) convst rd cs zeroing switches d1/(d out ) note: pin names in parentheses refer to serial mode d3/(sclk) v dd : 5v v ss : 0v for unipolar mode 5v for bipolar mode a in + a in v ref agnd dgnd 14 1418 bd + successive approximation register shift register ser/par mux applicatio n s i n for m atio n wu u u conversion details the ltc1418 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit parallel or serial output. the adc is complete with a precision reference and an internal clock. the control logic provides easy interface to micro- processors and dsps (please refer to digital interface section for the data format). conversion start is controlled by the cs and convst inputs. at the start of the conversion the successive approximation register (sar) is reset. once a conversion cycle has begun it cannot be restarted. during the conversion, the internal differential 14-bit capacitive dac output is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). 1418 f01 output latch sar c dac + c dac v dac v dac + + comp d13 d0 14 hold hold hold a in + a in zeroing switches c sample c sample + hold sample sample figure 1. simplified block diagram
9 ltc1418 applicatio n s i n for m atio n wu u u referring to figure 1, the a in + and a in C inputs are con- nected to the sample-and-hold capacitors (c sample ) dur- ing the acquire phase and the comparator offset is nulled by the zeroing switches. in this acquire phase, a minimum delay of 1 m s will provide enough time for the sample-and- hold capacitors to acquire the analog signal. during the convert phase the comparator zeroing switches open, putting the comparator into compare mode. the input switches the c sample capacitors to ground, transferring the differential analog input charge onto the summing junction. this input charge is successively compared with the binary weighted charges supplied by the differential capacitive dac. bit decisions are made by the high speed comparator. at the end of a conversion, the differential dac output balances the a in + and a in C input charges. the sar contents (a 14-bit data word) which represent the difference of a in + and a in C are loaded into the 14-bit output latches. dynamic performance the ltc1418 has excellent high speed sampling capabil- ity. fft (fast fourier transform) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algo- rithm, the adcs spectral content can be examined for frequencies outside the fundamental. figure 2 shows a typical ltc1418 fft plot. signal-to-noise ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 2a shows a typical spectral content with a 200khz sampling rate and a 10khz input. the dynamic performance is excellent for input frequencies up to and beyond the nyquist limit of 100khz. frequency (khz) 01030507090 amplitude (db) 0 20 40 60 80 100 120 20 40 60 80 1418 f02a 100 f sample = 200khz f in = 9.9609375khz sfdr = 99.32 sinad = 82.4 figure 2a. ltc1418 nonaveraged, 4096 point fft, input frequency = 10khz frequency (khz) 01030507090 amplitude (db) 0 20 40 60 80 100 120 20 40 60 80 1418 f02b 100 f sample = 200khz f in = 97.509765khz sfdr = 94.29 sinad = 81.4 figure 2b. ltc1418 nonaveraged, 4096 point fft, input frequency = 97.5khz effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to the s/(n + d) by the equation: n = [s/(n + d) C 1.76]/6.02 where n is the effective number of bits of resolution and s/(n + d) is expressed in db. at the maximum sampling rate of 200khz the ltc1418 maintains near ideal enobs up to the nyquist input frequency of 100khz (refer to figure 3).
10 ltc1418 applicatio n s i n for m atio n wu u u figure 3. effective bits and signal/(noise + distortion) vs input frequency shown in figure 4. the ltc1418 has good distortion performance up to the nyquist frequency and beyond. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (fa + fb). if the two input sine waves are equal in magni- tude, the value (in decibels) of the 2nd order imd products can be expressed by the following formula: imd fa fb log amplitude + () = () 20 at fa + fb amplitude at fa total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd log vvv vn v = +++ 20 234 1 222 2 ... where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. thd vs input frequency is figure 4. distortion vs input frequency input frequency (hz) amplitude (db below the fundamental) 0 20 40 60 80 100 120 1418 g03 1k 100k 1m 10k thd 2nd 3rd peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal. frequency (khz) 0 120 amplitude (db) 100 ?0 ?0 ?0 20 50 70 100 1418 g05 ?0 0 10 30 40 60 80 90 f sample = 200khz f in1 = 97.65625khz f in2 = 104.248046khz figure 5. intermodulation distortion plot input frequency (hz) 1k efective bits 14 13 12 11 10 9 8 7 6 5 4 3 2 10k 100k 1m 1418 f03
11 ltc1418 applicatio n s i n for m atio n wu u u full-power and full-linear bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input signal. the full-linear bandwidth is the input frequency at which the s/(n + d) has dropped to 77db (12.5 effective bits). the ltc1418 has been designed to optimize input band- width, allowing the adc to undersample input signals with frequencies above the converters nyquist frequency. the noise floor stays very low at high frequencies; s/(n + d) becomes dominated by distortion at frequencies far beyond nyquist. driving the analog input the differential analog inputs of the ltc1418 are easy to drive. the inputs may be driven differentially or as a single- ended input (i.e., the a in C input is grounded). the a in + and a in C inputs are sampled at the same instant. any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample- and-hold circuit. the inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. during conversion, the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low then the ltc1418 inputs can be driven directly. as source impedance increases so will acquisition time (see figure 6). for minimum acquisition time, with high source impedance, a buffer amplifier must be used. the only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts 1 m s for full throughput rate. choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, choose an amplifier that has a low output impedance (<100 w ) at the closed-loop bandwidth frequency. for example, if an amplifier is used in a gain of 1 and has a closed-loop bandwidth of 10mhz, then the output impedance at 10mhz must be less than 100 w . the second requirement is that the closed-loop bandwidth must be greater than 5mhz to ensure adequate small-signal settling for full throughput rate. if slower op amps are used, more settling time can be provided by increasing the time between conversions. the best choice for an op amp to drive the ltc1418 will depend on the application. generally, applications fall into two categories: ac applications where dynamic specifica- tions are most critical and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the ltc1418. more detailed information is available in the linear technology databooks and on the linearview tm cd-rom. lt ? 1354: 12mhz, 400v/ m s op amp. 1.25ma maximum supply current. good ac and dc specifications. suitable for dual supply application. lt1357: 25mhz, 600v/ m s op amp. 2.5ma maximum supply current. good ac and dc specifications. suitable for dual supply application. lt1366/lt1367: dual/quad precision rail-to-rail input and output op amps. 375 m a supply current per amplifier. 1.8v to 15v supplies. low input offset voltage: 150 m v. good for low power and single supply applications with sampling rates of 20ksps and under. lt1498/lt1499: 10mhz, 6v/ m s, dual/quad rail-to-rail input and output op amps. 1.7ma supply current per figure 6. t acq vs source resistance source resistance ( w ) 1 acquisition time ( m s) 10 1 100 1k 10k 1418 f06 0.1 10 100 100k linearview is a trademark of linear technology corporation.
12 ltc1418 applicatio n s i n for m atio n wu u u amplifier. 2.2v to 15v supplies. good ac performance, input noise voltage = 12nv/ ? hz (typ). lt1630/lt1631: 30mhz, 10v/ m s, dual/quad rail-to-rail input and output precision op amps. 3.5ma supply current per amplifier. 2.7v to 15v supplies. best ac performance, input noise voltage = 6nv/ ? hz (typ), thd = C 86db at 100khz. input filtering the noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the ltc1418 noise and distortion. the small-signal band- width of the sample-and-hold circuit is 5mhz. any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for many applications. for example, figure 7 shows a 2000pf capacitor from + a in to ground and a 100 w source resistor to limit the input bandwidth to 800khz. the 2000pf capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the adc input from sam- pling glitch sensitive circuitry. high quality capacitors and resistors should be used since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. input range the 2.048v and 0v to 4.096v input ranges of the ltc1418 are optimized for low noise and low distortion. most op amps also perform well over these ranges, allowing direct coupling to the analog inputs and eliminat- ing the need for special translation circuitry. some applications may require other input ranges. the ltc1418 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. the following sections describe the reference and input circuitry and how they affect the input range. internal reference the ltc1418 has an on-chip, temperature compensated, curvature corrected, bandgap reference which is factory trimmed to 2.500v. it is internally connected to a reference amplifier and is available at pin 3. a 8k resistor is in series with the output so that it can be easily overdriven in applications where an external reference is required, see figure 8. the reference amplifier compensation pin (refcomp, pin 4) must be connected to a capacitor to ground. the reference is stable with capacitors of 1 m f or greater. for the best noise performance, a 10 m f in parallel with a 0.1 m f ceramic is recommended. the v ref pin can be driven with a dac or other means to provide input span adjustment. the reference should be kept in the range of 2.25v to 2.75v for specified linearity. ltc1418 a in + a in ? v ref refcomp agnd analog input 100 1418 f07 1 2 3 4 5 2000pf 10 m f figure 7. rc input filter analog input 5v 1418 f08 10 m f 0.1 m f v in v out lt1460 1 2 3 4 5 ltc1418 5v a in + a in ? v ref refcomp agnd v dd figure 8. using the lt1460 as an external reference
13 ltc1418 applicatio n s i n for m atio n wu u u figure 9a. ltc1418 unipolar transfer characteristics analog input 1418 f10a 5v r4 100 w r2 50k r3 24k r7 48k r6 24k r1 50k r5 47k 0.1 m f 10 m f r8 100 w 1 2 3 4 5 ltc1418 a in + a in ? v ref refcomp agnd v ss v dd figure 10a. offset and full-scale adjust circuit if C 5v is not available unipolar / bipolar operation and adjustment figure 9a shows the ideal input/output characteristics for the ltc1418. the code transitions occur midway between successive integer lsb values (i.e., 0.5lsb, 1.5lsb, 2.5lsb, fs C 1.5lsb). the output code is natural binary with 1lsb = fs/16384 = 4.096v/16384 = 250 m v. figure 9b shows the input/output transfer characteristics for the bipolar mode in twos complement format. unipolar offset and full-scale error adjustment in applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. offset error must be adjusted before full-scale error. figures 10a and 10b show the extra components required for full- scale error adjustment. zero offset is achieved by adjust- ing the offset applied to the a in C input. for zero offset error apply 125 m v (i.e., 0.5lsb) at the input and adjust the offset at the a in C input until the output code flickers between 0000 0000 0000 00 and 0000 0000 0000 01. for full-scale adjustment, an input voltage of 4.095625v (fs C 1.5lsbs) is applied to a in + and r2 is adjusted until the output code flickers between 1111 1111 1111 10 and 1111 1111 1111 11. bipolar offset and full-scale error adjustment bipolar offset and full-scale errors are adjusted in a similar fashion to the unipolar case. again, bipolar offset error must be adjusted before full-scale error. bipolar offset figure 9b. ltc1418 bipolar transfer characteristics figure 10b. offset and full-scale adjust circuit if C 5v is available input voltage (v) 0v output code ? lsb 1418 f9b 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fs/2 ?1lsb fs/2 fs = 4.096v 1lsb = fs/16384 analog input 1418 f10b 5v ?v ?v 1n5817 r4 100 w r2 50k r3 24k r6 24k r1 50k r5 47k 0.1 m f * *only needed if v ss goes above ground 10 m f 1 2 3 4 5 ltc1418 a in + a in ? v ref refcomp agnd v ss v dd input voltage (v) 0v output code fs ?1lsb 1418 f9a 111...111 111...110 111...101 111...100 000...000 000...001 000...010 000...011 1 lsb unipolar zero 1lsb = fs 16384 4.096v 16384 =
14 ltc1418 applicatio n s i n for m atio n wu u u nected to this analog ground plane. low impedance ana- log and digital power supply common returns are essential to low noise operation of the adc and the foil width for these tracks should be as wide as possible. in applications where the adc data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. these errors are due to feedthrough from the microprocessor to the successive approximation comparator. the problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buff- ers to isolate the adc data bus. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc1418 has differential inputs to minimize noise coupling. common mode noise on the a in + and a in C leads will be rejected by the input cmrr. the a in C input can be used as a ground sense for the a in + input; the ltc1418 will hold and convert the difference voltage between a in + and a in C . the leads to a in + (pin 1) and a in C (pin 2) should be kept as short as possible. in applications where this is not possible, the a in + and a in C traces should be run side by side to equalize coupling. supply bypassing high quality, low series resistance ceramic, 10 m f bypass capacitors should be used at the v dd and refcomp pins. surface mount ceramic capacitors such as murata grm235y5v106z016 provide excellent bypassing in a small board space. alternatively 10 m f tantalum capacitors in parallel with 0.1 m f ceramic capacitors can be used. error adjustment is achieved by adjusting the offset applied to the a in C input. for zero offset error apply C 125 m v (i.e., C 0.5lsb) at a in + and adjust the offset at the a in C input until the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. for full-scale adjustment, an input voltage of 2.047625v (fs C 1.5lsbs) is applied to a in + and r2 is adjusted until the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11. board layout and grounding wire wrap boards are not recommended for high resolu- tion or high speed a/d converters. to obtain the best performance from the ltc1418, a printed circuit board with ground plane is required. the ground plane under the adc area should be as free of breaks and holes as possible, such that a low impedance path between all adc grounds and all adc decoupling capacitors is provided. it is critical to prevent digital noise from being coupled to the analog input, reference or analog power supply lines. layout should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track. an analog ground plane separate from the logic system ground should be established under and around the adc. pin 5 (agnd) and pin 14 (dgnd) and all other analog grounds should be connected to this single analog ground plane. the refcomp bypass capacitor and the v dd by- pass capacitor should also be connected to this analog ground plane. no other digital grounds should be con- 1418 f11 digital system analog input circuitry 5 4 2 27 28 14 1 10 f 3 1 f10 f 10 f analog ground plane + a in + agnd refcomp v ss v ref v dd ltc1418 dgnd a in figure 11. power supply grounding practice
15 ltc1418 figure 12a. suggested evaluation circuit schematic applicatio n s i n for m atio n wu u u v logic + +v in gnd a + a agnd dgnd gnd v cc v cc v cc v cc v ss jp4 v logic r14 20 w 0.125w u4 ltc1418 b[00:13] u5 74hc574 u6 74hc574 13 12 7 14 51 13 19 6 20 7 en1 en2 dgnd header 6-pin hc14 hc14 u7f 74hc244 98 hc14 u7d j6-13 j6-14 j6-11 j6-12 j6-9 j6-10 j6-7 j6-8 j6-5 j6-6 j6-3 j6-4 j6-1 j6-2 j6-15 j6-16 j6-17 j6-18 d13 d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d13 rdy d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d13 rdy dgnd dgnd led jp1 d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d00 d01 d02 d03 d04 d05 d06 d07 d08 d09 d10 d11 d12 d13 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d[00:13] r0, 1k r1 r2 r3 r4 r5 r6 r8 r7 r9 r10 r11 r12 r13 header 18-pin 11 10 hc14 r21 1k v logic v logic d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d12 d11 d10 d09 d08 d07 d06 d00 d01 d02 d03 d04 d05 d13 19 18 17 16 15 14 13 12 19 18 17 16 15 14 13 12 q0 q1 q2 q3 q4 q5 q6 q7 q0 q1 q2 q3 q4 q5 q6 q7 0e 0e data ready dual supply select single notes: unless otherwise specified 1. all resistor values in ohms, 1/10w, 5% 2. all capacitor values in f, 25v, 20% and in pf, 50v, 10% v cc v ss clk j7 v in u2 lt1121-5 d15 ss12 r17 10k r18 10k r19 51 w r16 51 w r15 51 w r22 1m jp5c cs ser/par shdn hc14 hc14 c11 1000pf c8 1 m f 16v c13 10 m f 16v c9 10 f 16v jp6 jp7 c6 15pf c5 10 f 16v c2 22 f 10v c10 10 f 10v c1 22 f 10v c12 0.1 f c14 0.1 f gnd tabgnd 1 24 3 c4 0.1 m f c3 0.1 m f u3 lt1363 v v + 2 3 1 23 4 6 7 8 1 4 j3 7v to 15v j4 jp2 j5 jp3 v out v out j2 1 2 3 4 25 24 23 22 21 28 26 27 5 14 6 7 8 9 10 11 12 13 15 16 17 18 19 20 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 b00 b01 b02 b03 b04 b05 b13 b12 b11 b10 b09 b08 b07 b06 1 11 2 3 4 5 6 7 8 9 1 11 2 3 4 5 6 7 8 9 jp5b jp5a v logic 4 18 15 17 16 2 j8-5 j8-4 j8-3 j8-1 j8-2 j8-6 5 u8b 74hc244 74hc244 74hc244 1 9 b00 b01 b02 b03 b04 ext/int d out clkout sclk extclkin u8e u8h 74hc244 74hc244 u8g 74hc244 c7 0.1 f c15 0.1 f + + v ss j1 7v to 15v d14 ss12 ? in 2 4 1 3 u1 lt1175-5 + 1418 f12a r20 19k v in v out tab gnd u7c u7g hc14 u8f u8a 12 8 u8d 14 6 74hc244 u8c r23 100k u7b u7a u7e d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 +a in ? in v ref refcomp cs convst rd shdn ser/par v dd busy v ss agnd dgnd
16 ltc1418 applicatio n s i n for m atio n wu u u figure 12b. suggested evaluation circuit board component side top silkscreen figure 12c. suggested evaluation circuit boardtop layer 1418 f12b 1418 f12c
17 ltc1418 applicatio n s i n for m atio n wu u u figure 12d. suggested evaluation circuit boardsolder side layout 1418 f12d bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. example layout figures 12a, 12b, 12c and 12d show the schematic and layout of a suggested evaluation board. the layout demon- strates the proper use of decoupling capacitors and ground plane with a 2-layer printed circuit board. digital interface the ltc1418 can operate in serial or parallel mode. in parallel mode the adc is designed to interface with micro- processors as a memory mapped device. the cs and rd control inputs are common to all peripheral memory interfacing. in serial mode only four digital interface lines are required, sclk, convst, extclkin and d out . sclk, the serial data shift clock can be an external input or supplied by the ltc1418 internal clock. internal clock the adc has an internal clock. in parallel output mode the internal clock is always used as the conversion clock. in serial output mode either the internal clock or an external clock may be used as the conversion clock (see figure 20). the internal clock is factory trimmed to achieve a typical conversion time of 3.4 m s and a maximum conversion time over the full operating temperature range of 4 m s. no exter- nal adjustments are required, and with the guaranteed maxi- mum acquisition time of 1 m s, throughput performance of 200ksps is assured. power shutdown the ltc1418 provides two power shutdown modes, nap and sleep, to save power during inactive periods. the nap mode reduces the power by 80% and leaves only the digital logic and reference powered up. the wake-up time from nap to active is 500ns (see figure 13a). in sleep mode all bias currents are shut down and only leakage current remains about 2 m a. wake-up time from sleep
18 ltc1418 applicatio n s i n for m atio n wu u u figure 14. cs to convst set-up timing t 2 t 1 cs convst rd 1418 f14 mode is much slower since the reference circuit must power up and settle to 0.005% for full 14-bit accuracy. sleep mode wake-up time is dependent on the value of the capacitor connected to the refcomp (pin 4). the wake-up time is 30ms with the recommended 10 m f capacitor. shutdown is controlled by pin 22 (shdn); the adc is in shutdown when it is low. the shutdown mode is selected with pin 25 (cs); low selects nap (see figure 13b), high selects sleep. t 4 shdn convst 1418 f13a figure 13a. shdn to convst wake-up timing t 3 cs shdn 1418 f13b figure 13b. cs to shdn timing conversion control conversion start is controlled by the cs and convst inputs. a falling edge of convst pin will start a conversion after the adc has been selected (i.e., cs is low, see figure 14). once initiated, it cannot be restarted until the conver- sion is complete. converter status is indicated by the busy output. busy is low during a conversion. data output the data format is controlled by the ser/par input pin; logic low selects parallel output format. in parallel mode the 14-bit data output word d0 to d13 is updated at the end of each conversion on pins 6 to 13 and pins 15 to 20. a logic high applied to ser/par selects the serial formatted data output and pins 16 to 20 assume their serial function, pins 6 to 13 and 15 are in the hi-z state. in either parallel or serial data formats, outputs will be active only when cs and rd are low. any other combination of cs and rd will three-state the output. in unipolar mode (v ss = 0v) the data will be in straight binary format (corresponding to the unipolar input range). in bipolar mode (v ss = C 5v), the data will be in twos complement format (corresponding to the bipolar input range). parallel output mode parallel mode is selected with a logic 0 applied to the ser/par pin. figures 15 through 19 show different modes of parallel output operation. in modes 1a and 1b (figures 15 and 16) cs and rd are both tied low. the falling edge of convst starts the conversion. the data outputs are always enabled and data can be latched with the busy rising edge. mode 1a shows operation with a narrow logic low convst pulse. mode 1b shows a narrow logic high convst pulse. in mode 2 (figure 17) cs is tied low. the falling edge of convst signal again starts the conversion. data outputs are in three-state until read by the mpu with the rd signal. mode 2 can be used for operation with a shared databus. in slow memory and rom modes (figures 18 and 19), cs is tied low and convst and rd are tied together. the mpu starts the conversion and reads the output with the rd signal. conversions are started by the mpu or dsp (no external sample clock). in slow memory mode the processor takes rd (= convst) low and starts the conversion. busy goes low forcing the processor into a wait state. the previous conversion result appears on the data outputs. when the conversion is complete, the new conversion results appear on the data
19 ltc1418 applicatio n s i n for m atio n wu u u figure 15. mode 1a. convst starts a conversion. data outputs always enabled (convst = ) figure 16. mode 1b. convst starts a conversion. data outputs always enabled (convst = ) data (n ?1) db13 to db0 convst busy 1418 f16 t conv t 5 t 6 t 13 t 7 data n db13 to db0 data (n + 1) db13 to db0 data cs = rd = 0 t 6 t 8 data (n ?1) db13 to db0 convst cs = rd = 0 busy 1418 f15 t 5 t conv (sample n) t 6 t 8 t 7 data n db13 to db0 data (n + 1) db13 to db0 data convst cs = 0 (sample n) busy 1418 f17 t 5 t conv t 8 t 12 t 6 t 9 t 12 data n db13 to db0 t 11 t 10 rd data figure 17. mode 2. convst starts a conversion. data is read by rd
20 ltc1418 applicatio n s i n for m atio n wu u u rd = convst cs = 0 busy 1418 f18 t conv (sample n) t 6 data (n ?1) db13 to db0 data data n db13 to db0 data (n + 1) db13 to db0 data n db13 to db0 t 11 t 8 t 10 t 7 figure 18. slow memory mode timing figure 19. rom mode timing rd = convst cs = 0 (sample n) busy 1418 f19 t conv t 6 data (n ?1) db13 to db0 data data n db13 to db0 t 10 t 11 t 8 outputs; busy goes high releasing the processor and the processor takes rd (= convst) back high and reads the new conversion data. in rom mode, the processor takes rd (= convst) low, starting a conversion and reading the previous conversion result. after the conversion is complete, the processor can read the new result and initiate another conversion. serial output mode serial output mode is selected when the ser/par input pin is high. in this mode, pins 16 to 20, d0 (ext/int), d1 (d out ), d2 (clkout), d3 (sclk) and d4 (extclkin) assume their serial functions as shown in figure 20. (during this discussion these pins will be referred to by their serial function names: ext/int, d out , clkout, sclk and extclkin.) as in parallel mode, conversions are started by a falling convst edge with cs low. after a conversion is completed and the output shift register has been updated, busy will go high and valid data will be available on d out (pin 19). this data can be clocked out either before the next conversion starts or it can be clocked out during the next conversion. to enable the serial data output buffer and shift clock, cs and rd must be low. figure 20 shows a function block diagram of the ltc1418 in serial mode. there are two pieces to this circuitry: the conversion clock selection circuit (ext/int, extclkin and clkout) and the serial port (sclk, d out , cs and rd). conversion clock selection (serial mode) in figure 20, the conversion clock controls the internal adc operation. the conversion clock can be either inter- nal or external. by connecting ext/int low, the internal clock is selected. this clock generates 16 clock cycles which feed into the sar for each conversion. to select an external conversion clock, tie ext/int high and apply an external conversion clock to extclkin (pin 16). (when an external shift clock (sclk) is used during a conversion, the sclk should be used as the external conversion clock to avoid the noise generated by the
21 ltc1418 applicatio n s i n for m atio n wu u u three state buffer three state buffer 23 rd 17 ?? sclk* cs 25 extclkin* 16 ext/int* busy *pins 16 to 20 are labeled with their serial functions 1418 f20 20 d out * 19 clkout* 18 26 shift register internal clock 16 conversion clock cycles eoc data in 14 data out clock input ?? sar figure 20. functional block diagram for serial mode (ser/par = high) asynchronous clocks. to maintain accuracy the external conversion clock frequency must be between 30khz and 4.5mhz.) the sar sends an end of conversion signal, eoc, that gates the external conversion clock so that only 16 clock cycles can go into the sar, even if the external clock, extclkin, contains more than 16 cycles. when cs and rd are low, these 16 cycles of conversion clock (whether internally or externally generated) will appear on clkout during each conversion and then clkout will remain low until the next conversion. if desired, clkout can be used as a master clock to drive the serial port. because clkout is running during the conversion, it is important to avoid excessive loading that can cause large supply transients and create noise. for the best performance, limit clkout loading to 20pf. serial port the serial port in figure 20 is made up of a 16-bit shift register and a three-state output buffer that are con- trolled by three inputs: sclk, rd and cs. the serial port has one output, d out , that provides the serial output data. the sclk is used to clock the shift register. data may be clocked out with the internal conversion clock operating as a master by connecting clkout (pin 18) to sclk (pin 17) or with an external data clock applied to d3 (sclk). the minimum number of sclk cycles required to transfer a data word is 14. normally, sclk contains 16 clock cycles for a word length of 16 bits; 14 bits with msb first, followed by two trailing zeros. a logic high on rd disables sclk and three-states d out . in case of using a continuous sclk, rd can be controlled to limit the number of shift clocks to the desired number (i.e., 16 cycles) and to three-state d out after the data transfer. a logic high on cs three-states the d out output buffer. it also inhibits conversion when it is tied high. in power shutdown mode (shdn = low), a high cs selects sleep mode while a low cs selects nap mode. for normal serial port operation, cs can be grounded. d out outputs the serial data; 14 bits, msb first, on the falling edge of each sclk (see figures 21 and 22). if 16 sclks are provided, the 14 data bits will be followed by
22 ltc1418 applicatio n s i n for m atio n wu u u figure 22. internal conversion clock selected. data transferred during conversion using the adc clock output as a master shift clock (sclk driven from clkout) two zeros. the msb (d13) will be valid on the first rising and the first falling edge of the sclk. d12 will be valid on the second rising and the second falling edge as will all the remaining bits. the data may be captured on either edge. the largest hold time margin is achieved if data is captured on the rising edge of sclk. busy gives the end of conversion indication. when the ltc1418 is configured as a master serial device, busy can be used as a framing pulse and to three-state the t 15 t 14 sclk v il v oh v ol d out 1418 f21 figure 21. sclk to d out delay ltc1418 busy (= rd) clkout ( = sclk) busy convst convst rd sclk clkout ext/int d out 26 24 23 17 18 20 25 19 d out cs 1418 f22a m p or dsp (configured as slave) or shift register d12 d11 d11 d12 capture on rising clock d13 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 fill zeros d13 1 t 5 t 6 2345678910111213141516 123 d13 d13 d12 d11 hi-z hi-z data n data (n ?1) (sample n) (sample n + 1) d out cs = ext/int = 0 clkout (= sclk) convst t 13 t conv t 8 sample hold hold t 10 t 7 t 11 1418 f22b busy (= rd) t 15 t 14 clkout (= sclk) v il v oh v ol d out capture on falling clock
23 ltc1418 applicatio n s i n for m atio n wu u u clock and the sclk. the internal clock has been optimized for the fastest conversion time, consequently this mode can provide the best overall speed performance. to select an internal conversion clock, tie ext/int (pin 20) low. the internal clock appears on clkout (pin 18) which can be tied to sclk (pin 17) to supply the sclk. using external clock for conversion and data transfer . in figure 23, data from the previous conversion is output during the conversion with an external clock providing both the conversion clock and the shift clock. to select an external conversion clock, tie ext/int high and apply the figure 23. external conversion clock selected. data transferred during conversion using the external clock (external clock drives both extclkin and sclk) serial port after transferring the serial output data by tying it to the rd pin. figures 22 to 25 show several serial modes of operation, demonstrating the flexibility of the ltc1418 serial port. serial data output during a conversion using internal conversion clock for conversion and data transfer . figure 22 shows data from the previous conversion being clocked out during the conversion with the ltc1418 internal clock providing both the conversion d12 d11 d11 d12 capture on rising clock d13 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 fill zeros d13 1 t 5 t 6 t 10 2345678910111213141516 123 d13 d13 d12 d11 hi-z hi-z data n data (n ?1) (sample n) (sample n + 1) d out cs = 0, ext/int = 5 extclkin (= sclk) convst t 13 t conv t 8 sample hold hold t dextclkin t 7 t 11 1418 f23b busy (= rd) t 15 t 14 t lextclkin t hextclkin extclkin (= sclk) v il v oh v ol d out capture on falling clock ltc1418 busy (= rd) extclkin ( = sclk) busy convst convst rd extclkin sclk ext/int d out d out cs 5v 25 20 19 26 24 17 16 23 1418 f23a m p or dsp
24 ltc1418 applicatio n s i n for m atio n wu u u clock to extclkin. the same clock is also applied to sclk to provide a data shift clock. to maintain accuracy the conversion clock frequency must be between 30khz and 4.5mhz. it is not recommended to clock data with an external clock during a conversion that is running on an internal clock because the asynchronous clocks may create noise. serial data output after a conversion using internal conversion clock and external data clock . in this mode, data is output after the end of each conver- sion but before the next conversion is started (figure 24). the internal clock is used as the conversion clock and an external clock is used for the sclk. this mode is useful in applications where the processor acts as a master serial device. this mode is spi and microwire compatible. it ltc1418 busy convst 26 24 19 20 25 23 17 convst rd sclk ext/int d out cs 1418 f24a m p or dsp int c0 sck miso 1211109876543210 fill zeros d13 t 5 t 6 12345678910111213141516 hi-z data n hi-z (sample n) d out cs = ext/int = 0 convst t 13 t conv t 8 hold sample t 9 t 10 1418 f24b t 11 busy sclk rd d11 d12 capture on rising clock d13 t 15 t 14 t lsclk t hsclk sclk v il v oh v ol d out capture on falling clock figure 24. internal conversion clock selected. data transferred after conversion using an external sclk. busy - indicates end of conversion
25 ltc1418 applicatio n s i n for m atio n wu u u also allows operation when the sclk frequency is very low (less than 30khz). to select the internal conversion clock tie ext/int low. the external sclk is applied to sclk. rd can be used to gate the external sclk, such that data will clock only after rd goes low and to three-state d out after data transfer. if more than 16 sclks are provided, more zeros will be filled in after the data word indefinitely. ltc1418 busy convst convst rd extclkin sclk ext/int d out cs 5v 25 16 24 23 17 26 19 20 1418 f25a m p or dsp clkout int c0 sck miso t 5 t 6 12345678910111213141516 cs = 0, ext/int = 5 convst extclkin t 13 t dextclkin t 8 hold sample t 9 t 7 t 11 busy sclk rd 12345678910111213141516 1 2 34 1211109876543210 fill zeros d13 hi-z data n hi-z (sample n) d out t conv t 10 1418 f25b d11 d12 capture on rising clock d13 t 15 t 14 sclk v il v oh v ol d out capture on falling clock t lsclk t hsclk figure 25. external conversion clock selected. data transferred after conversion using an external sclk. busy - indicates end of conversion using external conversion clock and external data clock . in figure 25, data is also output after each conver- sion is completed and before the next conversion is started. an external clock is used for the conversion clock and either another or the same external clock is used for the sclk. this mode is identical to figure 24 except that an external clock is used for the conversion. this mode
26 ltc1418 applicatio n s i n for m atio n wu u u package descriptio n u dimensions in inches (millimeters) unless otherwise noted. g28 ssop 0694 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212** (5.20 ?5.38) 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8 9 10 11 12 14 13 0.397 ?0.407* (10.07 ?10.33) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) dimensions do not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimensions do not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) allows the user to synchronize the a/d conversion to an external clock either to have precise control of the internal bit test timing or to provide a precise conversion time. as in figure 24, this mode works when the sclk frequency is very low (less than 30khz). however, the external conver- sion clock must be between 30khz and 4.5mhz to maintain accuracy. if more than 16 sclks are provided, more zeros will be filled in after the data word indefinitely. to select the external conversion clock tie ext/int high. the external sclk is applied to sclk. rd can be used to gate the external sclk such that data will clock only after rd goes low.
27 ltc1418 package descriptio n u dimensions in inches (millimeters) unless otherwise noted. n package 28-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) n28 1197 0.255 0.015* (6.477 0.381) 1.370* (34.789) max 34 5 6 7 8 9 10 11 12 21 13 14 15 16 18 17 19 20 22 23 24 25 26 2 27 1 28 0.020 (0.508) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.005 (0.127) min 0.100 0.010 (2.540 0.254) 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
28 ltc1418 ? linear technology corporation 1998 1418f lt/tp 0798 4k ? printed in usa typical applicatio n u single 5v supply, 200khz, 14-bit sampling a/d converter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a in + a in v ref refcomp agnd d13(msb) d12 d11 d10 d9 d8 d7 d6 dgnd v dd v ss busy cs convst rd shdn ser/par (ext/int)d0 (d out )d1 (clkout)d2 (sclk)d3 (extclkin )d4 d5 ltc1418 10 m f 1 m f differential analog input (0v to 4.096v) 10 m f 1n5817* *required only if v ss can become positive with respect to ground 5v 14-bit parallel bus m p control lines 1418 ta03 v ref output 2.5v related parts part number description comments adcs ltc1274/ltc1277 low power, 12-bit, 100ksps adcs 10mw power dissipation, parallel/byte interface ltc1412 12-bit, 3msps sampling adc best dynamic performance, sinad = 72db at nyquist ltc1415 single 5v, 12-bit, 1.25msps adc 55mw power dissipation, 72db sinad ltc1416 low power, 14-bit, 400ksps adc 70mw power dissipation, 80.5db sinad ltc1419 low power, 14-bit, 800ksps adc true 14-bit linearity, 81.5db sinad, 150mw dissipation ltc1604 16-bit, 333ksps sampling adc 2.5v input, sinad = 90db, thd = 100db ltc1605 single 5v, 16-bit, 100ksps adc low power, 10v inputs, parallel/byte interface dacs ltc1595 16-bit cmos multiplying dac in so-8 1lsb max inl/dnl, 1nv ? sec glitch, dac8043 upgrade ltc1596 16-bit cmos multiplying dac 1lsb max inl/dnl, dac8143/ad7543 upgrade reference lt1019-2.5 precision bandgap reference 0.05% max, 5ppm/ c max linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com

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